Issue: The Perceived Impact of IC Component Level ESD Specifications to System Level Reliability
Synopsis: Ever since the Industry Council published the white paper on ESD Target Levels, recommending a reduction of the component levels to more realistic and safe values for HBM and MM ESD, there have been other articles inferring that this action would increase the system level exposure and susceptibility to ESD. Some OEMs and system board manufacturers have reacted by saying that they would continue to require the previous levels (a la 2kV HBM) since there is no proof that following the Industry Council’s recommendation would guarantee the system reliability to ESD. These arguments, while understandable, unfortunately miss the main points.
The Council’s Response: When a component is qualified it is tested for its vulnerability to IC handling in production areas. Once it is placed on a board the test requirements and the protection approaches fall into a different category. A component level protection designer cannot anticipate how each system is built. ESD robustness for both System Level and Component Level is equally important, but the issues and strategies are distinct, requiring different design approaches. For some years now billions of IC components at less than 2kV HBM, even at 500V have been shipped with no increase in field return rates which are mostly only associated with electrical overstress (EOS). This is as expected since a reliable component once in the system does not see the pin combination stress scenario as tested according to the HBM or MM stress methods. Some examples to this effect have been collected by the Council and have been documented in the white paper. It is also worth noting that in a system board with several ICs, any residual charges coming from other devices with external ports after an IEC pulse have been found to have minimal impact. This gives again the additional assurance that the component level reduction to 1kV or 500V would have no impact on the system. If there is vulnerability it would be for the direct pins exposed with an external interface. The protection for these types of pins is tested with the IEC method at the system level (IEC standard 61000-4-2), when the IC is mounted in the application board. Both the waveform and the test methodology for the IEC stress testing are significantly different than those for HBM and MM testing of IC components. This fact, and the lack of field returns showing any correlation between HBM or MM levels and system level ESD failures, means that a change of component ESD target levels will have no effect on system level ESD failures. Meeting passing criterion for the IEC test requires either the design of external clamp circuitry, or very robust protection devices on-chip, but only for exposed pins. There is also the additional misunderstanding that designing 8kV or 15kV HBM protection for these exposed pins would ensure passing the customer’s system requirement. This level of component level HBM performance, albeit at a very high level, does not always translate into the system level IEC passing performance for exposed pins. Therefore, system level reliability invariably involves a co-design effort.
The above explanation is offered because board manufacturers unfortunately tend to have the wrong impression that as long as 2kV HBM devices are endlessly supplied there would be no system problems and if any component level is reduced the problem instantly falls on them. The Council would like to emphasize again that this has not been the case, nor is there any proof that this would be the case going forward. More system level ESD standards and design techniques are needed and thus more effort and focus should shift towards this strategy.
The Council’s Request: The Council welcomes system engineers to post their questions and concerns through this web site. Maintaining ESD reliability is important and takes the responsibility of all parties. By the same token, all other electronics suppliers and OEMs are also invited to send any concerns on these or any other issues.
Synopsis: Ever since the Industry Council published the white paper on ESD Target Levels, recommending a reduction of the component levels to more realistic and safe values for HBM and MM ESD, there have been other articles inferring that this action would increase the system level exposure and susceptibility to ESD. Some OEMs and system board manufacturers have reacted by saying that they would continue to require the previous levels (a la 2kV HBM) since there is no proof that following the Industry Council’s recommendation would guarantee the system reliability to ESD. These arguments, while understandable, unfortunately miss the main points.
The Council’s Response: When a component is qualified it is tested for its vulnerability to IC handling in production areas. Once it is placed on a board the test requirements and the protection approaches fall into a different category. A component level protection designer cannot anticipate how each system is built. ESD robustness for both System Level and Component Level is equally important, but the issues and strategies are distinct, requiring different design approaches. For some years now billions of IC components at less than 2kV HBM, even at 500V have been shipped with no increase in field return rates which are mostly only associated with electrical overstress (EOS). This is as expected since a reliable component once in the system does not see the pin combination stress scenario as tested according to the HBM or MM stress methods. Some examples to this effect have been collected by the Council and have been documented in the white paper. It is also worth noting that in a system board with several ICs, any residual charges coming from other devices with external ports after an IEC pulse have been found to have minimal impact. This gives again the additional assurance that the component level reduction to 1kV or 500V would have no impact on the system. If there is vulnerability it would be for the direct pins exposed with an external interface. The protection for these types of pins is tested with the IEC method at the system level (IEC standard 61000-4-2), when the IC is mounted in the application board. Both the waveform and the test methodology for the IEC stress testing are significantly different than those for HBM and MM testing of IC components. This fact, and the lack of field returns showing any correlation between HBM or MM levels and system level ESD failures, means that a change of component ESD target levels will have no effect on system level ESD failures. Meeting passing criterion for the IEC test requires either the design of external clamp circuitry, or very robust protection devices on-chip, but only for exposed pins. There is also the additional misunderstanding that designing 8kV or 15kV HBM protection for these exposed pins would ensure passing the customer’s system requirement. This level of component level HBM performance, albeit at a very high level, does not always translate into the system level IEC passing performance for exposed pins. Therefore, system level reliability invariably involves a co-design effort.
The above explanation is offered because board manufacturers unfortunately tend to have the wrong impression that as long as 2kV HBM devices are endlessly supplied there would be no system problems and if any component level is reduced the problem instantly falls on them. The Council would like to emphasize again that this has not been the case, nor is there any proof that this would be the case going forward. More system level ESD standards and design techniques are needed and thus more effort and focus should shift towards this strategy.
The Council’s Request: The Council welcomes system engineers to post their questions and concerns through this web site. Maintaining ESD reliability is important and takes the responsibility of all parties. By the same token, all other electronics suppliers and OEMs are also invited to send any concerns on these or any other issues.
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